Engage and lead graphics SW architecture and development from concept to production. Influence the hardware architecture with concrete data and feedback from the GPU programming research work. Drive innovation by staying current with the latest advancements in GPU industry standards and trends. Define, design, and scope GPU software architecture which brings the best out

Work with circuit architects for the implementation of various PHY AMS macros, blocks, and components. Own small to medium size complexity AMS macro designs. Work with IP leads/managers following management priorities, design direction and guidelines, deliver quality macro design meeting specs within schedule. Work with layout and physical design activities to meet IP PPA

Review microarchitectural specifications to analyze hardware IP for potential security weaknesses. Develop a threat model that includes the security scope, potential vulnerabilities, attack vectors, and risk mitigation strategies based on AMD's state of the art security technologies. Develop and implement security verification test plan and define security coverage/sign o

Develop software in C++, Python, HIP, assembly to enable key mathematical operations on GPU Design GPU computational software libraries for AI, HPC applications Aid management in planning, and delivering industry leading software Carry out performance optimizations for important use cases to maximize hardware utilization in pre silicon and post silicon environments Suppor

High Speed PCB Design development Develop routing strategies for new IP including, PCIe, DP, Memory, XGMI Stackup creation and high speed material selection. Strategizing with a variety of teams including, SI, EMI, PI, Thermal and Mechanical Development of Design rules Aiding in the development of New Tools and Processes Developing ASIC ball outs Experience in memory, HDI

Provide advisement and coordination for RPPG leadership team to drive decision making processes and execution of the strategic business objectives. Develop collaterals (presentations, pre reads, communications) for the CVP on internal and external activities through original contribution and/or collaboration with executives and senior leaders across RPPG. Represent the CV

Serve as the AMD technical owner of various 3 rd party SERDES and other mixed signal IP. Provide pre and post silicon IP leadership and support for SerDes PHYs and other mixed signal IP, in particular IP like PCIe, Ethernet, UCIe, USB, MIPI, and Display PHYs, plus PLLs and miscellaneous IOs and circuits. Work directly with 3 rd party IP vendors to support design transfer,